ISL6592 Datasheet, PDF (16/21 Pages) Intersil Corporation – 6-Phase Digital Multiphase Controller

ISL6592
low, or high impedance. If the input signal is high, the gate
driver turns the high-side switch on. If the input signal is low,
the gate driver turns the low-side switch on. If the input
signal is three-state, the driver does not turn either high-side
or low-side switches on and the power stage is high
impedance or three-stated. Non-overlap circuitry matched to
the switch FETs characteristics must be incorporated in the
FET driver.
For dual output configurations, two independent driver
circuits are implemented for the high side and low side.
Three-stating the output stage only requires both the PWM
and NDRIVE signals to be held logic low. ISL6592
incorporates programmable non-overlap delay, with
separate rising edge and falling edge delays, so that the dual
driver does not require non-overlap logic.
The output drive signals are generated using a 3.3V tri-
valent driver. All outputs are three-stated during reset,
configuration, and inactive state. This allows the user to set
the appropriate level to three-state the power stage, using
external pull-up or pull-down resistors. ISL6592 also
supports independent polarity control on each output,
allowing any polarity driver to be used.
ISL6592 supporst various output configurations as shown in
the Table 3 below.
OUT
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
TABLE 3. PROGRAMMABLE OUTPUT CONFIGURATION
NON-SCRAMBLED OUTPUTS (pwm_scramble = 0)
# OF PHASES FOR SINGLE PWM OUTPUTS (dual = 0) # OF PHASES FOR DUAL PWM/NDRIVE OUTPUTS (dual = 1)
2
3
4
5
6
2
3
4
5
6
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
hi-Z
pwm3
pwm3
pwm3
pwm3
hi-Z
pwm3
pwm3
pwm3
pwm3
hi-Z
hi-Z
pwm4
pwm4
pwm4
ndr1
ndr1
ndr1
ndr1
ndr1
hi-Z
hi-Z
hi-Z
pwm5
pwm5
ndr2
ndr2
ndr2
ndr2
ndr2
hi-Z
hi-Z
hi-Z
hi-Z
pwm6
hi-Z
ndr3
ndr3
ndr3
ndr3
hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) pwm4
pwm4
pwm4
hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl)
ndr4
ndr4
ndr4
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrh) pwm5
pwm5
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrl)
ndr5
ndr5
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrh) pwm6
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrl)
ndr6
OUT
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
SCRAMBLED OUTPUTS (pwm_scramble = 1)
# OF PHASES FOR SINGLE PWM OUTPUTS (dual = 0) # OF PHASES FOR DUAL PWM/NDRIVE OUTPUTS (dual = 1)
2
3
4
5
6
2
3
4
5
6
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
pwm1
hi-Z
hi-Z
pwm4
pwm4
pwm4
ndr1
ndr1
ndr1
ndr1
ndr1
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
pwm2
hi-Z
hi-Z
hi-Z
pwm5
pwm5
ndr2
ndr2
ndr2
ndr2
ndr2
hi-Z
pwm3
pwm3
pwm3
pwm3
hi-Z
pwm3
pwm3
pwm3
pwm3
hi-Z
hi-Z
hi-Z
hi-Z
pwm6
hi-Z
ndr3
ndr3
ndr3
ndr3
hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) hi-Z (atrh) pwm4
pwm4
pwm4
hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl) hi-Z (atrl)
ndr4
ndr4
ndr4
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrh) pwm5
pwm5
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrl)
ndr5
ndr5
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrh) pwm6
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z
hi-Z (atrl)
ndr6
16
FN9163.1
August 5, 2005