ISL12020MIRZ-T7A Datasheet, PDF (18/34 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving

ISL12020M
BATTERY VOLTAGE TRIP VOLTAGE REGISTER
(PWR_VBAT)
This register controls the trip points for the two V_BAT alarms, with
levels set to approximately 85% and 75% of the nominal battery
level.
TABLE 8.
ADDR 7
6
5
4
3
2
1
0
0Ah D RESEALB VB85T VB85T VB85T VB75T VB75T VB75T
p2 p1 p0 p2 p1 p0
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting V_BAT pin from the
internal circuitry. Setting this bit allows the device to disconnect the
battery and eliminate standby current drain while the device is
unused. Once V_DD is powered up, this bit is reset and the V_BAT pin is
then connected to the internal circuitry.
The application for this bit involves placing the chip on a board
with a battery and testing the board. Once the board is tested
and ready to ship, it is desirable to disconnect the battery to keep
it fresh until the board or unit is placed into final use. Setting
RESEALB = “1” initiates the battery disconnect, and after V_DD
power is cycled down and up again, the RESEAL bit is cleared to
“0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)
Three bits select the first alarm (85% of Nominal V_BAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal battery voltage level.
See Table 9.
VB85Tp2
0
0
0
0
1
1
1
TABLE 9. VB85T ALARM LEVEL
VB85Tp1
VB85Tp0
BATTERY ALARM TRIP
LEVEL
(V)
0
0
2.125
0
1
2.295
1
0
2.550
1
1
2.805
0
0
3.060
0
1
4.250
1
0
4.675
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
Three bits select the second alarm (75% of Nominal V_BAT) level for
the battery voltage monitor. There are total of 7 levels that could be
selected for the second alarm. Any of the of levels could be selected
as the second alarm with no reference as to nominal Battery voltage
level. See Table 10.
TABLE 10. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM TRIP
LEVEL
(V)
0
0
0
1.875
0
0
1
2.025
0
1
0
2.250
0
1
1
2.475
1
0
0
2.700
1
0
1
3.750
1
1
0
4.125
Initial AT and DT setting Register (ITRO)
These bits are used to trim the initial error (at room temperature)
of the crystal. Both Digital Trimming (DT) and Analog Trimming
(AT) methods are available. The digital trimming uses clock pulse
skipping and insertion for frequency adjustment. Analog
trimming uses load capacitance adjustment to pull the oscillator
frequency. A range of +62.5ppm to -61.5ppm is possible with
combined digital and analog trimming.
Initial values for the ITR0 register are preset internally and
recalled to RAM registers on power-up. These values can be
overwritten by the user although this is not suggested as the
resulting temperature compensation performance will be
compromised. Aging adjustment is normally a few ppm and can
be handled by writing to the IATR section.
AGING AND INITIAL TRIM DIGITAL TRIMMING BITS
(IDTR0<1:0>)
These bits allow ±30.5ppm initial trimming range for the crystal
frequency. This is meant to be a coarse adjustment if the range
needed is outside that of the IATR control. See Table 11. The
IDTR0 register should only be changed while the TSE (Temp
Sense Enable) bit is “0”.
The ISL12020M has a preset Initial Digital Trimming value
corresponding to the crystal in the module. This value is recalled
on initial power-up and should never be changed for best
temperature compensation performance, although the user may
change this preset value to adjust for aging or board mounting
changes if so desired.
IDTR01
0
0
1
1
TABLE 11. IDTR0 TRIMMING RANGE
IDTR00
TRIMMING RANGE
0
Default/Disabled
1
+30.5ppm
0
0ppm
1
-30.5ppm
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0<5:0>)
The Initial Analog Trimming Register allows +32ppm to -31ppm
adjustment in 1ppm/bit increments. This enables fine frequency
18
FN6667.5
December 13, 2011