82567 Datasheet, PDF (8/33 Pages) Intel Corporation – GbE Physical Layer Transceiver (PHY)

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82567—Datasheet
LCI Interface Pins
Signal Name
JKCLK
JRSTSYNC
JTXD2
JTXD1
JTXD0
JRXD2
JRXD1
JRXD0
Pin
45
50
44
43
42
49
48
47
Type
O
I
I
O
Description
LCI/GLCI Clock
The clock is driven by the 82567 according to the operation
mode:
In 1000 Mb/s mode, JKCLK frequency is 62.5 MHz.
In 100 Mb/s mode, JKCLK frequency is 50 MHz.
In 10 Mb/s mode and no link, JKCLK frequency is 5 MHz.
In power down mode, JKCLK frequency is 0 MHz.
Reset/SYNC
This pin is driven by the MAC and has two functions:
Reset. When this pin is asserted beyond one LCI clock, the
82567 refers to this signal as a reset signal. However, to ensure
that the 82567 resets, the reset should remain active for at least
1ms. This functionality is also used to bring the 82567 out of a
power-down state.
SYNC. When this pin is activated synchronously for one LCI clock
only, it is used for synchronization between the MAC and the
82567 on LCI word boundaries.
LCI Transmit Data
These pins are used for receiving real time control and
management data transmitted by the ICH9 LAN. These pins are
also used to move out of band control from the MAC to the
82567. The pins should be fully synchronous to JKCLK.
LCI Receive Data
These pins are used for transmitting real time control and
management data received by the ICH9 LAN. These pins are also
used to move out of band control from the 82567 to the MAC.
Miscellaneous Pins
Signal Name
IEEE_TEST_P
IEEE_TEST_N
Pin
12
13
LAN_DISABLE_N 37
RSET
15
RESERVED_NC 51
Type
Description
A-out
I/PU
Positive side of the high speed differential debug port for the 82567.
When this pin is set, the 82567 consumes minimum power and is
disabled.
This pin should be connected through 4.99 kohm, +-1%, to ground.
Do not connect.
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