82567 Datasheet, PDF (14/33 Pages) Intel Corporation – GbE Physical Layer Transceiver (PHY)

82567—Datasheet
3.2.5
3.2.5.1
LPLU is controlled through the LPLU bit in the PHY Power Management register. The
MAC sets and clears the bit according to hardware/software settings. The 82567 auto-
negotiates with the updated LPLU setting on the following auto-negotiation operation.
The 82567 does not automatically auto-negotiate after a change in the LPLU value.
LPLU is not dependent on whether the system is in AC or DC mode . In S0 state, Link
Speed Battery Saver overrides the LPLU funtionality.
LPLU is enabled for Non-D0a states by GbE NVM image word 17h (bit 10)
• 0b = Low Power Link Up is disabled.
• 1b = Low Power Link Up is enabled in all non-D0a states.
LPLU power consumption depends on what speed it negotiates at. This datasheet
includes all of the power numbers for the 82567 in the various speeds; see section 4.6,
Tables 1-4.
LAN Disable
82567 has a LAN_DISABLE_N input pin that can be used by the BIOS to disable the
PHY. The addition of this feature simplifies the PHY disable feature from the BIOS
relative to the LAN Disable sequence used in 82566.
LAN_DISABLE_N is an active low input and when asserted, it loses all functionality
other than the ability to power up again. Asserting LAN_DISABLE_N causes:
• GLCI enters electrical idle
• JKCLK is stopped to the MAC
• 25MHz clock remains active
• 82567 tri-states its output buffers
• WOL is not supported
On de-assertion:
• PHY sends JKCLK to MAC; MAC asserts JRSTSYNC
• PHY goes through usual initialization process.
Important Note:
Be sure to check for the latest LAN Disable and LAN_PHY_PWR_CTRL design guidelines.
The information in the Specification Updates listed below supercedes the general LAN
disable recommendations below.
Depending on which I/O Control Hub you are connecting, the information can be found
in the errata section of the following documents:
• I/O Controller Hub 9 (ICH9) Family Specification Update
• I/O Controller Hub 10 (ICH10) Family Specification Update
General LAN Disable Recommendations
LAN_DISABLE_N needs to be connected to the GPIO12/LAN_PHY_PWR_CTRL output of
ICH9, ICH9M, or ICH10. The GPIO12 needs to configured using ICH soft straps as
LAN_PHY_PWR_CTRL (bit [20] of STRP0 register - LAN_PHY_PWR_CTRL/GPIO12
Select (LAN_PHY_PWR_GPIO12_SEL) set to “1.” This can be done with the Intel FIT
tool by setting LAN_PHY_PWR_CTRL in ICH STRP0 to native mode (“1”). Please refer
to ICH9 EDS Section 22.2.5.1 for more details.
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