82567 Datasheet, PDF (28/33 Pages) Intel Corporation – GbE Physical Layer Transceiver (PHY)

82567—Datasheet
4.8
4.8.1
Table 10.
Timing Parameters
Timing Requirements
The 82567 requires the following start-up and power state transitions.
Timing Requirements
4.8.2
Table 11.
Parameter
T_{JRST_min}
Tc2dud
Tr2init
Description
Min
Minimum duration of
JRSTSYNC pulse
Completion of dock/undock
configuration following cable
connection
Completion of PHY
configuration following a reset
complete indication
1 ms
Max
0.5 sec
0.5 sec
Notes
Per LCI specification
Timing Guarantees
The 82567 guarantees the following start-up and power state transition related timing
parameters.
Timing Guarantees
Parameter
Description
Min
T_{PHY_Reset}
Reset de-assertion to PHY
reset complete
T_XTAL
T_POR
T_JKCLK
T_{TX_IDLE-TO-DIFF-DATA}
T_{RX_IDLE-TO-DIFF-DATA}
T_c2an
XTAL frequency stable after
platform power ramp up
Internal POR trigger after XTAL
stable
JKCLK output stable after
internal POR
Maximum time to transition to
valid TX specifications after
leaving an electrical idle
condition
Maximum time to be ready to
accept data after leaving an
electrical idle condition
Cable connect to start of auto
negotiation
1.2 s
Max
10 ms
5 ms
1 s
3 s
200 ns
200 ns
1.3 s
Notes
PHY configuration
should be delayed
until PHY completes
its reset
Required by GLCI
2.0 specification
Required by GLCI
2.0 specification
Per 802.3
specification
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