82567 Datasheet, PDF (19/33 Pages) Intel Corporation – GbE Physical Layer Transceiver (PHY)

Datasheet—82567
4.5
Table 5.
Oscillator Specifications
Oscillator Specifications and Timing Requirements
Parameter Name
Frequency
Swing
Frequency Tolerance
Temperature Stability
Operating Temperature
Aging
Coupling capacitor
Calibration mode
Oscillator Load
Capacitance
Shunt Capacitance
Series Resistance, Rs
Drive Level
Insulation Resistance
T_{H_XTAL_IN}
T_{L_XTAL_IN}
T_{R_XTAL_IN}
T_{F_XTAL_IN}
T_{J_XTAL_IN}
Symbol/
Parameter
f
V_P-P
f/f_o
T_opr
f/f_o
C_coupling
Parallel
Conditions Min
Typ
Max
@25 °C]
3
-20 to +70
0 C to 70 C
-20 to +70 °C
12
25.0
3.3
3.6
±30
±30
±5 ppm
per year
15
18
18
@ 100 VDC
XTAL_IN High Time
XTAL_IN Low Time
XTAL_IN Rise
10%-90%
XTAL_IN Fall
10%-90%
XTAL_IN Total
Jitter
500
13
20
13
20
6
50
300
5
5
200¹
Unit
MHz
V
ppm
ppm
ppm
pF
pF
pF

W
M
ns
ns
ns
ns
ps
1 Broadband peak-peak=200pS, Broadband rms=3pS, 12 kHzto 20 MHz rms= 1ps
4.5.1
Oscillator High Voltage Configuration
This configuration involves capacitor C1, which forms a capacitor divider with Cstray of
about 20 pF. This attenuates the input clock amplitude and adjusts the clock oscillator
load capacitance.
19