82567 Datasheet, PDF (20/33 Pages) Intel Corporation – GbE Physical Layer Transceiver (PHY)

82567—Datasheet
Note:
Note:
Note:
Vin = VDD * (C1/(C1 + Cstray))
Vin = 3.3 * (C1/(C1 + Cstray))
This enables load clock oscillators of 15 pF to be used. If the value of Cstray is unknown,
C1 should be adjusted by tuning the input clock amplitude to approximately 1.2-1.8
Vptp. If Cstray equals 20 pF, then C1 is 15 pF ±10%. A low capacitance, high impedance
probe (C < 1 pF, R > 500 K_) should be used for testing. Probing the parameters can
affect the measurement of the clock amplitude and cause errors in the adjustment. A
test should also be done after the probe has been removed for circuit operation. If jitter
performance is poor, a lower jitter clock oscillator can be implemented.
oCf^stt^rh^aye
shown
board
in the figure
capacitance
below
and is
is not an actual discrete capacitor, but
not to be placed in the actual design.
a
representation
Measure the Vptp at the XTAL1 pin to ensure that it is never over 1.8 V. Overvoltage
could lead to a silicon reliability concern.
Keep C1 close to the XTAL1 pin of the 82567. This will help make the value of Cstray
less dependent on the PCB (Total Cstray is a combination of Cstray of PCB and Cstray of
silicon).
4.6
Power Consumption
The following table lists the measured values for the 82567’s power. The numbers apply
to the 82567 power dissipation with External Voltage Regulators (EVRs). Power is
reduced according to link speed and link activity.
20