82567 Datasheet, PDF (10/33 Pages) Intel Corporation – GbE Physical Layer Transceiver (PHY)

82567—Datasheet
Note:
2.6
JTAG_TRST
35
I
JTAG Reset
JTAG_TMS
39
I/PU JTAG TMS Input
TEST_EN
Test Mode Enable
36
T/s _{This signal enables test mode capabilities. It should be strapped}
to GND for normal operation.
The 82567 uses the JTAG interface to support XOR files for manufacturing test. BSDL is
not supported.
Power Supply Pins
Signal Name
VCC3_3
VCC1_05
VCC1_8
Pin
3
28
46
5
8
33
38
11
14
18
19
24
25
30
41
32
54
CTRL10
31
CTRL18
29
DIS_REG1_0
34
Type
Description
P
3.3 VDC Supply
This is connected to the 82567.
P
1.05 V DC Supply
This is connected to the 82567.
1.8 V-1.9 V DC Supply
P
This is connected to the 82567. 82567 supports both 1.8 V and
1.9 V for this DC supply.
1.05 V Control
Out
This is the voltage control signal for the external PNP transistor
that generates the 1.05 V supply.
1.8 V-1.9 V Control
Out
This is the voltage control signal for the external PNP transistor.
The default voltage generated from the external PNP is 1.9 V.
When set to 3.3 V, configured to use external regulator for 1.05
A
V supply. When set to 0, the internal regulator will be used for
1.05 V supply. A 1 kOhm pull up or 1 kOhm pull down resistor is
required, depending on the desired configuration.
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