BX80557430SL9XN Datasheet, PDF (69/100 Pages) Intel Corporation – Intel® Celeron® Processor 400 Series

Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 4 of 9))
Name
DEFER#
DRDY#
Type
Description
Input
DEFER# is asserted by an agent to indicate that a transaction
cannot be guaranteed in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/output
agent. This signal must connect the appropriate pins/lands of all
processor FSB agents.
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP[3:0]#
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Input/
Output
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FCx
FERR#/PBE#
GTLREF[1:0]
Other
FC signals are signals that are available for compatibility with other
processors.
Output
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
For additional information on the pending break event functionality,
including the identification of support of the feature and enable/
disable information, refer to volume 3 of the Intel Architecture
Software Developer's Manual and the Intel Processor Identification
and the CPUID Instruction application note.
Input
GTLREF[1:0] determine the signal reference level for GTL+ input
signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
Datasheet
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