BX80557430SL9XN Datasheet, PDF (34/100 Pages) Intel Corporation – Intel® Celeron® Processor 400 Series

Electrical Specifications
2.9
Table 19.
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
PECI DC Electrical Limits
Symbol
Definition and Conditions
V_in
V_hysteresis
V_n
V_p
I_source
I_sink
I_leak+
I_leak-
C_bus
V_noise
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V_OH = 0.75 * V_TT)
Low level output sink
(V_OL = 0.25 * V_TT)
High impedance state leakage to V_TT
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above 300 MHz
Min
-0.15
0.1 * V_TT
0.275 * V_TT
0.550 * V_TT
-6.0
0.5
N/A
N/A
—
0.1 * V_TT
Max
V_TT+ 0.15
—
0.500 * V_TT
0.725 * V_TT
Units Notes
V
V
3
V
V
N/A
mA
1.0
mA
50
µA
2
10
µA
2
10
pF
4
—
V_p-p
NOTE:
1.
V_TT supplies the PECI interface. PECI behavior does not affect V_TT min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
The input buffers use a Schmitt-triggered input design for improved noise immunity.
4.
One node is counted for each client and one node for the system host. Extended trace
lengths might appear as additional nodes.
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Datasheet