BX80557430SL9XN Datasheet, PDF (23/100 Pages) Intel Corporation – Intel® Celeron® Processor 400 Series

Electrical Specifications
2.7.1
Table 8.
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 8 identifies which signals are common clock, source synchronous,
and asynchronous.
FSB Signal Groups (Sheet 1 of 2)
Signal Group
Type
Signals¹
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#
GTL+ Source
Synchronous to
Synchronous I/O assoc. strobe
Signals
REQ[4:0]#, A[16:3]#³
A[35:17]#³
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
GTL+ Strobes
CMOS
Open Drain
Output
Open Drain
Input/Output
FSB Clock
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#,
BSEL[2:0], VID[6:1]
FERR#/PBE#, IERR#, THERMTRIP#, TDO
Clock
PROCHOT#⁴
BCLK[1:0], ITP_CLK[1:0]²
Datasheet
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