IA80C152 Datasheet, PDF (20/32 Pages) InnovASIC, Inc – UNIVERSAL COMMUNICATIONS CONTROLLER

Page 20 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1 - Timer overFlow 1 interrupt flag set by hardware when timer 1 overflows. Hardware clears this flag when the
processor vectors to the interrupt service routine.
TR1 - Timer Run 1 flag set by software to turn on timer 1 and cleared by software to turn off timer 1.
TF0 - Timer overFlow 0 interrupt flag set by hardware when timer 0 overflows. Hardware clears this flag when the
processor vectors to the interrupt service routine.
TR0 - Timer Run 0 flag set by software to turn on timer 0 and cleared by software to turn off timer 0.
IE1 - Interrupt External 1 flag set by hardware when an edge is detected on External Interrupt 1. Hardware clears
this flag when the processor vectors to the interrupt service routine.
IT1 - Interrupt Trigger 1 flag is set by software to specify a falling edge triggered interrupt for External Interrupt 1.
The flag is cleared by software to specify a low level triggered interrupt for External Interrupt 1.
IE0 - Interrupt External 0 flag set by hardware when an edge is detected on External Interrupt 0. Hardware clears
this flag when the processor vectors to the interrupt service routine.
IT0 - Interrupt Trigger 0 flag is set by software to specify a falling edge triggered interrupt for External Interrupt 0.
The flag is cleared by software to specify a low level triggered interrupt for External Interrupt 0.
TFIFO (085h) - This is the 3 byte buffer used for storing transmit data. If TEN is set to a 1 transmission begins as soon
as data is written to TFIFO.
TH0, TL0 (08Ch, 08Ah) - These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These
registers may be used together or separately depending on Timer 0 mode bits.
TH1, TL1 (08Dh, 08Bh) - These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These
registers may be used together or separately depending on Timer 0 mode bits.
TMOD (089h) - This register controls the set up and modes of Timers 0 and 1 as defined by the table below.
7
6
5
4
3
2
1
0
Timer 1
Timer 0
GATE
C/Tn
M1
M0
GATE
C/Tn
M1
M0
GATE - When this bit is set, Timers/Counters may be turned on or off by the corresponding External Interrupt, if
the appropriate TR bit is set. When this bit is cleared, Timers/Counters may only be turned on or off by the
appropriate TR bit.
C/Tn - Counter/Timer flag. Set by software for Counter operation, cleared by software for Timer operation.
M1, M0 - Set the mode of the Timers/Counters as defined by the table below.
Mode
M1
0
0
1
0
2
1
3
1
M0
Description
0
13-bit Timer
1
16-bit Timer/Counter
0
8-bit Auto Reload Timer/Counter
1
One 8-bit Timer/Counter (TL0) controlled by Timer 0 control bits.
One 8-bit Timer/Counter (TH0) controlled by Timer 1 control bits.
TSTAT* (0D8h) - This register provides status of the GSC transmitter as defined below.
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