IA80C152 Datasheet, PDF (18/32 Pages) InnovASIC, Inc – UNIVERSAL COMMUNICATIONS CONTROLLER

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IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
PSW* (0D0h) - The Program Status Word register provides arithmetic and other microcontroller status as well as control
for the selection of register banks 0 through 4.
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
-
P
CY - Carry Flag set to 1 if an instruction execution results in a carry.
AC - Auxiliary Carry Flag set to 1 if an instruction execution results in a carry.
F0 - Flag 0 available for user defined general purpose.
RS1, RS0 - Register bank Select 1 bit and Register bank Select 0 bit in combination define the current register bank to
be used by the microprocessor. See table below.
Register Bank
RS1
0
0
1
0
2
1
3
1
RS0
Register Bank Addresses
0
00h-07h
1
08h-0Fh
0
10h-17h
1
18h-1fh
OV - The OVerflow bit indicates an arithmetic overflow when set to a 1.
P - Parity flag set or cleared by the hardware each instruction to indicate odd or even number of 1's in the
accumulator.
RFIFO (0F4h) - This is a 3 byte buffer which points to the oldest data in the buffer. The buffer is loaded with receive
data every time the receiver receives a new byte of data.
RSTAT* (0E8h) - This register provides status of the GSC receiver as defined below.
7
6
5
OR
RCABT
AE
4
CRCE
3
RDN
2
RFNE
1
GREN
HABEN - The Hardware Based Acknowledge Enable when set to a 1 enables this feature.
0
HABEN
GREN - When this bit is set the receiver is enabled to accept incoming frames. RFIFO should be cleared before
setting this bit by reading RFIFO until RFNE = 0. This should be done since setting GREN to a 1 clears RFIFO. It
takes twelve clock cycles for the status of RFNE to be updated after a read of RFIFO. Setting GREN also clears
RDN, CRCE, AE and RCABT. GREN is cleared by hardware at the end of a reception or if receive errors are
encountered. The user is responsible for setting this bit to a 1. The user or the GSC can set this bit to a 0. In
CSMA/CD mode the status of GREN has no effect on whether the receiver detects a collision since the receiver
always monitors the receive pin.
RFNE - This bit if set indicates that the receive FIFO is not empty. This flag is controlled by the GSC. If all the data
is read from the FIFO the GSC will clear the bit.
RDN - This bit is controlled by the GSC and if set indicates a successful receive operation has occurred. This bit will
not be set if a CRC, alignment, abort, or FIFO overrun error occurred.
CRCE - This bit is controlled by the GSC and if set indicates that a properly aligned frame was received without a
mismatched CRC.
AE - This bit is set by the GSC in CSMA/CD mode to indicate that the receiver shift register is not full and the CRC
is bad when the EOF was detected. If the CRC is correct AE will not be set and a misalignment will be assumed to
be caused by ‘dribble bits’as the line went idle. In SDLC mode AE is set if a non-byte aligned flag is received. CRCE
may also be set.
RCABT - This bit is set by the GSC when a collision is detected after data has been loaded into the receive FIFO in
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