IA80C152 Datasheet, PDF (16/32 Pages) InnovASIC, Inc – UNIVERSAL COMMUNICATIONS CONTROLLER

Page 16 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
EGSRE - Enable or disable GSC Receive Error interrupt.
EGSRV - Enable or disable GSC Receive Valid interrupt.
IFS (0A4h) - The Interframe Spacing register determines the number of bit times between transmitted frames in both
CSMA/CD and SDLC. Only even bit times can be used. The number written to this register is divided by two and
loaded into the seven most significant bits. An interframe space is created by counting down this seven bit number twice.
The value read from this register is the current count value in the upper seven bits and the first or second count down in
the LSB. A 1 indicates the first count down and a 0 indicates the second count down. The value may not be valid since
the register is clocked asynchronously to the CPU.
IP* (0B8h) - The Interrupt Priority register allows the software to select which interrupts have a higher than normal
priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the interrupt has a higher priority. When multiple bits
are set to higher priority, interrupts are resolved in the same order as their normal priority setting.
7
6
5
4
3
2
1
0
-
-
-
PS
PT1
PX1
PT0
PX0
PS - Set normal or higher priority level for serial port interrupt.
PT1 - Set normal or higher priority level for Timer 1 overflow interrupt.
PX1 - Set normal or higher priority level for External Interrupt 1.
PT0 - Set normal or higher priority level for Timer 0 overflow interrupt.
PX0 - Set normal or higher priority level for External Interrupt 0.
IPN1* (0F8h) - The Interrupt Enable Number 1 register allows the software to select which interrupts have a higher than
normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the interrupt has a higher priority. When
multiple bits are set to higher priority, interrupts are resolved in the same order as their normal priority setting.
7
6
5
4
3
2
1
0
-
-
PGSTE
PDMA1
PGSTV
PDMA0
PGSRE
PGSRV
PGSTE - Set normal or higher priority level for GSC Transmit Error interrupt.
PDMA1 - Set normal or higher priority level for DMA channel 1 interrupt.
PGSTV - Set normal or higher priority level for GSC Transmit Valid interrupt.
PDMA0 - Set normal or higher priority level for DMA channel 0 interrupt.
PGSRE - Set normal or higher priority level for GSC Receive Error interrupt.
PGSRV - Set normal or higher priority level for GSC Receive Valid interrupt.
MYSLOT (0F5h) - Register that controls the slot address for the devices as well as the type of Jam used and which
backoff algorithm is used during a collision.
7
6
5
4
3
2
1
0
DCJ
DCR
SA5
SA4
SA3
SA2
SA1
SA0
SA5-0 - The six slot address bits determine not only the address but also the priority. Addresses 0 through 63 are
available with 63 having the highest priority and 1 the lowest. An address of 0 will prevent a station from transmitting
during the collision resolution period.
DCR - The Deterministic Collision Resolution register determines which resolution algorithm to use. Setting this bit
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