IA80C152 Datasheet, PDF (15/32 Pages) InnovASIC, Inc – UNIVERSAL COMMUNICATIONS CONTROLLER

Page 15 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
CRC-CCITT is used.
AL - This bit determines the address length used. If set to a 1 the 16 bit addressing is used. If set to a 0 the 8 bit
addressing is used.
M1,M0 - These bits contain the backoff mode select bits as defined in the following table.
M1
M0
0
0
0
1
1
0
1
1
Mode
Normal
Raw Transmit
Raw Receive
Alternate Backoff
In Raw Receive mode the transmitter operates normally. The receiver operates normally except that all the bytes
following the BOF are loaded into the receive FIFO including the CRC.
In the Raw Transmit mode the receiver operates as normal and zero bit detection is performed. The transmit output
is driven from the receiver input. Data transmitted is done so without a preamble, flag or zero bit insertion and
without a CRC.
In the Alternate Backoff mode the backoff is modified so it is delayed until the end of the IFS. Since the IFS time is
generally longer than the slot time this should help to prevent collisions.
XTCLK - This bit enables the use of an external transmit clock. A 1 enables the external clock (input on port 1, bit 3),
a zero enables the internal baud rate generator.
IE* (0A8h) - The Interrupt Enable register allows the software to select which interrupts are enabled per the table below.
If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is enabled.
7
6
EA
-
5
4
3
2
1
0
-
ES
ET1
EX1
ET0
EX0
EA - Enable All interrupts. This bit globally enables or disables all interrupts regardless of the state of the individual
bits.
ES - Enable or disable serial port interrupt.
ET1 - Enable or disable Timer 1 overflow interrupt.
EX1 - Enable or disable External Interrupt 1.
ET0 - Enable or disable Timer 0 overflow interrupt.
EX0 - Enable or disable External Interrupt 0.
IEN1* (0C8h) - The Interrupt Enable Number 1 register allows the software to select which interrupts are enabled per
the table below. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is enabled.
7
6
5
4
3
2
1
0
-
-
EGSTE EDMA1 EGSTV EDMA0 EGSRE EGSRV
EGSTE - Enable or disable GSC Transmit Error interrupt.
EDMA1 - Enable or disable DMA channel 1 interrupt.
EGSTV - Enable or disable GSC Transmit Valid interrupt.
EDMA0 - Enable or disable DMA channel 0 interrupt.
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