XC2734X Datasheet, PDF (98/106 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2734X
XC2000 Family / Value Line
Electrical Parameters
Table 34 DAP Interface Timing for Lower Voltage Range
Parameter
DAP0 clock period¹⁾
DAP0 high time
DAP0 low time¹⁾
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t₁₁ SR 25
t₁₂ SR 8
t₁₃ SR 8
t₁₄ SR −
t₁₅ SR −
t₁₆ SR 6
Values
Typ. Max.
−
−
−
−
−
−
−
4
−
4
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns
DAP1 hold after DAP0 t₁₇ SR 6
−
−
ns
rising edge
DAP1 valid per DAP0
t₁₉ CC 12
17
−
ns
clock period²⁾
1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t₁₁
0.5 VDDP
t_{1 5}
t_{1 2}
t_{1 3}
Figure 23 Test Clock Timing (DAP0)
0.9 V_DDP
t₁₄
0.1 V_DDP
MC_DAP0
Data Sheet
98
V1.3, 2010-04