XC2734X Datasheet, PDF(28/106 Page) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

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XC2734X Datasheet, PDF (28/106 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

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XC2734X

XC2000 Family / Value Line

Functional Description

Table 7

XC2734X Memory Map (contâd)1)

Address Area

Start Loc. End Loc. Area Size2) Notes

Reserved for DSRAM 00â8000H 00â9FFFH 8 Kbytes

External memory area 00â0000H 00â7FFFH 32 Kbytes

1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate

external bus accesses.

2) The areas marked with â<â are slightly smaller than indicated, see column âNotesâ.

3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0âF000H to C0âFFFFH).

4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external

peripherals properly.

This common memory space consists of 16 Mbytes organized as 256 segments of

64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory

space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the

The internal data memory areas and the Special Function Register areas (SFR and

ESFR) are mapped into segment 0, the system segment.

The Program Management Unit (PMU) handles all code fetches and, therefore, controls

access to the program memories such as Flash memory and PSRAM.

The Data Management Unit (DMU) handles all data transfers and, therefore, controls

access to the DSRAM and the on-chip peripherals.

Both units (PMU and DMU) are connected to the high-speed system bus so that they can

exchange data. This is required if operands are read from program memory, code or

data is written to the PSRAM, code is fetched from external memory, or data is read from

or written to external resources. These include peripherals on the LXBus such as USIC

or MultiCAN. The system bus allows concurrent two-way communication for maximum

transfer performance.

Up to 16 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code

or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A

section of the PSRAM with programmable size can be write-protected.

Note: The actual size of the PSRAM depends on the quoted device type.

Data Sheet

V1.3, 2010-04

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