C167CS Datasheet, PDF (95/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C167CS
Derivatives
Interrupt and Trap Functions
5.2
Operation of the PEC Channels
The C167CS’s Peripheral Event Controller (PEC) provides 8 PEC service channels,
which move a single byte or word between two locations in segment 0 (data pages
3 … 0). This is the fastest possible interrupt response and in many cases is sufficient to
service the respective peripheral request (e.g. serial channels, etc.). Each channel is
controlled by a dedicated PEC Channel Counter/Control register (PECCx) and a pair of
pointers for source (SRCPx) and destination (DSTPx) of the data transfer.
The PECC registers control the action that is performed by the respective PEC channel.
PECCx
PEC Control Reg.
15 14 13 12
SFR (FECy_H/6z_H, see Table 5-4)
11 10 9 8 7 6 5 4
Reset Value: 0000_H
3210
-----
INC BWT
rw
rw
COUNT
rw
Bit
COUNT
BWT
INC
Function
PEC Transfer Count
Counts PEC transfers and influences the channel’s action (see Table 5-5)
Byte/Word Transfer Selection
0: Transfer a Word
1: Transfer a Byte
Increment Control (Modification of SRCPx or DSTPx)
0 0: Pointers are not modified
0 1: Increment DSTPx by 1 or 2 (BWT)
1 0: Increment SRCPx by 1 or 2 (BWT)
1 1: Reserved. Do not use this combination.
(changed to ‘10’ by hardware)
Table 5-4
Register
PECC0
PECC1
PECC2
PECC3
PEC Control Register Addresses
Address Reg. Space Register
FEC0_H/60_H
FEC2_H/61_H
FEC4_H/62_H
FEC6_H/63_H
SFR
SFR
SFR
SFR
PECC4
PECC5
PECC6
PECC7
Address
FEC8_H/64_H
FECA_H/65_H
FECC_H/66_H
FECE_H/67_H
Reg. Space
SFR
SFR
SFR
SFR
User’s Manual
5-12
V2.0, 2000-07