C167CS Datasheet, PDF (88/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C167CS
Derivatives
Interrupt and Trap Functions
Table 5-2 lists the vector locations for hardware traps and the corresponding status flags
in register TFR. It also lists the priorities of trap service for cases, where more than one
trap condition might be detected within the same instruction. After any reset (hardware
reset, software reset instruction SRST, or reset by watchdog timer overflow) program
execution starts at the reset vector at location 00’0000_H. Reset conditions have priority
over every other system activity and therefore have the highest priority (trap priority III).
Software traps may be initiated to any vector location between 00’0000_H and 00’01FC_H.
A service routine entered via a software TRAP instruction is always executed on the
current CPU priority level which is indicated in bit field ILVL in register PSW. This means
that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.
Table 5-2 Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector Trap
Trap
Location Number Prio
Reset Functions
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps
TRAP Instruction
–
RESET
RESET
RESET
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
UNDOPC BTRAP
PRTFLT BTRAP
ILLOPA BTRAP
ILLINA BTRAP
ILLBUS BTRAP
–
–
–
–
00’0000_H
00’0000_H
00’0000_H
00’0008_H
00’0010_H
00’0018_H
00’0028_H
00’0028_H
00’0028_H
00’0028_H
00’0028_H
[2C_H-3C_H]
Any
[00’0000_H-
00’01FC_H]
in steps
of 4_H
00_H
III
00_H
III
00_H
III
02_H
II
04_H
II
06_H
II
0A_H
I
0A_H
I
0A_H
I
0A_H
I
0A_H
I
[0B_H-0F_H]
Any
Current
[00_H-7F_H] CPU
Priority
User’s Manual
5-5
V2.0, 2000-07