C167CS Datasheet, PDF (230/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C167CS
Derivatives
The General Purpose Timer Units
All three timers of block GPT1 (T2, T3, T4) can run in 4 basic modes, which are timer,
gated timer, counter and incremental interface mode, and all timers can either count up
or down. Each timer has an alternate input function pin (TxIN) associated with it which
serves as the gate control in gated timer mode, or as the count input in counter mode.
The count direction (Up/Down) may be programmed via software or may be dynamically
altered by a signal at an external control input pin. Each overflow/underflow of core timer
T3 is latched in the toggle FlipFlop T3OTL and may be indicated on an alternate output
function pin. The auxiliary timers T2 and T4 may additionally be concatenated with the
core timer, or used as capture or reload registers for the core timer.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer registers T2, T3, or T4, which are located in the non-bitaddressable
SFR space. When any of the timer registers is written to by the CPU in the state
immediately before a timer increment, decrement, reload, or capture is to be performed,
the CPU write operation has priority in order to guarantee correct results.
T2EUD
f_CPU
T2IN
2ⁿ : 1
U/D
T2
Mode
Control
GPT1 Timer T2
Reload
Capture
f_CPU
T3IN
2ⁿ : 1
T3EUD
T4IN
f_CPU
T4EUD
2ⁿ : 1
T3
Mode
Control
GPT1 Timer T3
U/D
Toggle FF
T3OTL
Capture
Reload
T4
Mode
Control
GPT1 Timer T4
U/D
Figure 10-2 GPT1 Block Diagram
User’s Manual
10-2
Interrupt
Request
Interrupt
Request
T3OUT
Other
Timers
Interrupt
Request
MCT02141
n = 3 … 10
V2.0, 2000-07