English
Language : 

C167CS Datasheet, PDF (440/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller
C167CS
Derivatives
Power Management
21.1
Idle Mode
The power consumption of the C167CS microcontroller can be decreased by entering
Idle mode. In this mode all enabled peripherals, including the watchdog timer, continue
to operate normally, only the CPU operation is halted and the on-chip memory modules
are disabled.
Note: Peripherals that have been disabled via software also remain disabled after
entering Idle mode, of course.
Idle mode is entered after the IDLE instruction has been executed and the instruction
before the IDLE instruction has been completed (bitfield SLEEPCON in register
SYSCON1 must be ‘00B’). To prevent unintentional entry into Idle mode, the IDLE
instruction has been implemented as a protected 32-bit instruction.
Idle mode is terminated by interrupt requests from any enabled interrupt source whose
individual Interrupt Enable flag was set before the Idle mode was entered, regardless of
bit IEN.
For a request selected for CPU interrupt service the associated interrupt service routine
is entered if the priority level of the requesting source is higher than the current CPU
priority and the interrupt system is globally enabled. After the RETI (Return from
Interrupt) instruction of the interrupt service routine is executed the CPU continues
executing the program with the instruction following the IDLE instruction. Otherwise, if
the interrupt request cannot be serviced because of a too low priority or a globally
disabled interrupt system the CPU immediately resumes normal program execution with
the instruction following the IDLE instruction.
For a request which was programmed for PEC service a PEC data transfer is performed
if the priority level of this request is higher than the current CPU priority and the interrupt
system is globally enabled. After the PEC data transfer has been completed the CPU
remains in Idle mode. Otherwise, if the PEC request cannot be serviced because of a
too low priority or a globally disabled interrupt system the CPU does not remain in Idle
mode but continues program execution with the instruction following the IDLE
instruction.
User’s Manual
21-3
V2.0, 2000-07