C167CS Datasheet, PDF (19/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C167CS
Derivatives
Architectural Overview
2.1
Basic CPU Concepts and Optimizations
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate
multiply and divide unit, a bit-mask generator and a barrel shifter.
32
ROM
CPU
SP
STKOV
STKUN
Exec. Unit
Instr. Ptr.
Instr. Reg.
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
MDH
MDL
Mul/Div-HW
Bit-Mask Gen
ALU
(16-bit)
Barrel - Shifter
Context Ptr.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Page Ptr. Code Seg. Ptr.
R15
General
Purpose
Registers
R0
16
Internal
RAM
R15
R0
16
MCB02147
Figure 2-2 CPU Block Diagram
To meet the demand for greater performance and flexibility, a number of areas has been
optimized in the processor core. Functional blocks in the CPU core are controlled by
signals from the instruction decode logic. These are summarized below, and described
in detail in the following sections:
1) High Instruction Bandwidth/Fast Execution
2) High Function 8-bit and 16-bit Arithmetic and Logic Unit
3) Extended Bit Processing and Peripheral Control
4) High Performance Branch-, Call-, and Loop Processing
5) Consistent and Optimized Instruction Formats
6) Programmable Multiple Priority Interrupt Structure
User’s Manual
2-2
V2.0, 2000-07