C167CS Datasheet, PDF (301/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C167CS
Derivatives
The Watchdog Timer (WDT)
13
The Watchdog Timer (WDT)
To allow recovery from software or hardware failure, the C167CS provides a Watchdog
Timer. If the software fails to service this timer before an overflow occurs, an internal
reset sequence will be initiated. This internal reset will also pull the RSTOUT pin low,
which also resets the peripheral hardware which might be the cause for the malfunction.
When the watchdog timer is enabled and the software has been designed to service it
regularly before it overflows, the watchdog timer will supervise the program execution as
it only will overflow if the program does not progress properly. The watchdog timer will
also time out if a software error was due to hardware related failures. This prevents the
controller from malfunctioning for longer than a user-specified time.
Note: When the bidirectional reset is enabled also pin RSTIN will be pulled low for the
duration of the internal reset sequence upon a software reset or a watchdog timer
reset.
The watchdog timer provides two registers:
• a read-only timer register that contains the current count, and
• a control register for initialization and reset source detection.
Reset Indication Pins
RSTOUT
(deactivated by EINIT)
RSTIN
(bidirectional reset only)
Data Registers
WDT
Control Registers
WDTCON
MCA04381
Figure 13-1 SFRs and Port Pins Associated with the Watchdog Timer
The watchdog timer is a 16-bit up counter which is clocked with the prescaled CPU clock
(f_CPU). The prescaler divides the CPU clock:
• by 2 (WDTIN = ‘0’, WDTPRE = ‘0’), or
• by 4 (WDTIN = ‘0’, WDTPRE = ‘1’), or
• by 128 (WDTIN = ‘1’, WDTPRE = ‘0’), or
• by 256 (WDTIN = ‘1’, WDTPRE = ‘1’).
User’s Manual
13-1
V2.0, 2000-07