C167CS Datasheet, PDF (47/517 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C167CS
Derivatives
Memory Organization
XRAM Access via External Masters
In X-Peripheral Share mode (bit XPER-SHARE in register SYSCON is set) the on-chip
XRAM of the C167CS can be accessed by an external master during hold mode via the
C167CS’s bus interface. These external accesses must use the same configuration as
internally programmed (see above). No waitstates are required. In X-Peripheral Share
mode the C167CS bus interface reverses its direction, i.e. address lines (PORT1,
Port 4), control signals (RD, WR), and BHE must be driven by the external master.
Note: The configuration in register SYSCON cannot be changed after the execution of
the EINIT instruction.
User’s Manual
3-10
V2.0, 2000-07