HYB25D256800BT Datasheet, PDF (9/29 Pages) Infineon Technologies AG – 256MBit Double Data Rata SDRAM

Mode Register Operation
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0* 0*
Operating Mode
CAS Latency
BT
Burst Length
Mode Register
A12 - A9 A8 A7
0
00
0
10
0
01
-
--
A6 - A0
Valid
Valid
Operating Mode
Normal operation
Do not reset DLL
Normal operation
in DLL Reset
Reserved
Reserved
A3 Burst Type
0
Sequential
1
Interleave
CAS Latency
A6 A5 A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Latency
Reserved
Reserved
2
3 (optional)
Reserved
1.5 (optional)
2.5
Reserved
Burst Length
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
2003-01-10, V0.9
Page 9 of 29