HYB25D256800BT Datasheet, PDF (28/29 Pages) Infineon Technologies AG – 256MBit Double Data Rata SDRAM

HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C £ T_A £ 70 °C; V_DDQ = 2.6V ± 0.1V; V_DD = 2.6V ± 0.1V) (Part 2 of 2)
Symbol
Parameter
DDR400A
-5A
Min. Max.
DDR400B
-5
Min. Max.
Unit Notes
t_RCD Active to Read or Write delay
15
t_RP Precharge command period
15
t_RAP Active to Autoprecharge delay
15
t_RRD Active bank A to Active bank B command
10
t_WR Write recovery time
15
t_DAL
Auto precharge write recovery
+ precharge time
15
ns 1-4
15
ns 1-4
15
ns 1-4
10
ns 1-4
15
ns 1-4
t_CK 1-4,9
t_WTR Internal write to read command delay
1
1
t_CK 1-4
t_XSNR Exit self-refresh to non-read command
75
75
ns 1-4
t_XSRD Exit self-refresh to read command
200
200
t_CK 1-4
t_REFI
Average Periodic Refresh Interval (8192 refresh
commands per 64ms refresh period)
7.8
7.8 ms 1-4, 8
1. Input slew rate >= 1V/ns for DDR400
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the
input reference level for signals other than CK/CK, is V_REF. CK/CK slew rate are >= 1.0 V/ns
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics
(Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are
not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving
(LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time,
depending on t_DQSS.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual sys-
tem clock cycle time.
10. These parameters guarantee device timing, but they are not necessarilty tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew
rate >1.0 V/ns, measured between VOH(ac) and VOL(ac)
Page 28 of 29
2003-01-10, V0.9