HYB25D256800BT Datasheet, PDF (17/29 Pages) Infineon Technologies AG – 256MBit Double Data Rata SDRAM

HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Truth Table 2: Clock Enable (CKE)
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Current State
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
CKE n-1 CKEn
Previous
Cycle
L
Current
Cycle
L
L
H
L
L
L
H
H
L
H
L
H
L
H
H
Command n
Action n
X
Maintain Self-Refresh
Deselect or NOP
Exit Self-Refresh
X
Maintain Power-Down
Deselect or NOP
Exit Power-Down
Deselect or NOP
Precharge Power-Down Entry
AUTO REFRESH
Self Refresh Entry
Deselect or NOP
Active Power-Down Entry
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 18
Notes
1
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t_XSNR) period. A mini-
mum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
2003-01-10, V0.9
Page 17 of 29