HYB25D256800BT Datasheet, PDF (29/29 Pages) Infineon Technologies AG – 256MBit Double Data Rata SDRAM

HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Electrical Characteristics & AC Timing for DDR400 - Applicable Specifications
Expressed in Clock Cycles (0 °C £ T_A £ 70 °C; V_DDQ = 2.6V ± 0.1V; V_DD = 2.6V ± 0.1V,
Symbol
Parameter
t_MRD
t_WPRE
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RRD
t_WR
t_DAL
t_WTR
t_XSNR
t_XSRD
Mode register set command cycle time
Write preamble
Active to Precharge command
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
DDR400A/B
Min
Max
2
0.25
8
16000
11
13
3
3
2
3
5
1
10
200
Units
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
t_CK
Notes
1-54
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1-5
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK, is V_REF.
3. Inputs are not recognized as valid until V_REF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V_TT.
5. t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a spe-
cific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
2003-01-10, V0.9
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