HYB25D256800BT Datasheet, PDF (24/29 Pages) Infineon Technologies AG – 256MBit Double Data Rata SDRAM

HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
IDD Specification and Conditions
(0 °C £ T_A £ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V)
Symbol Parameter/Condition
DDR200 DDR266A DDR266
-8
-7
-7F
DDR333
-6
DDR400A/B
-5
Notes
Unit
typ. max. typ. max. typ. max. typ. max. typ. max.
4
Operating Current: one bank; active / precharge; tRC= tRCMIN; x4/x8
IDD0 DQ,DM,andDQSinputschangingonceperclockcycle;address
and control inputs changing once every two clock cycles
x16
70 90 75 100 83 110 85 110 90 115 mA
1, 2
72 95 77 105 86 115 88 115 100 120 mA
Operating Current: one bank; active/read/precharge;
x4/x8
80 100 90 110 98 120 100 120 105 125 mA
IDD1 burstlength4;
1, 2
Refer tothefollowingpagefor detailedtest conditions.
x16
83 105 94 115 102 125 104 125 115 135 mA
IDD2P
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE <= VIL MAX
57686869 6
9 mA 1,2
PrechargeFloatingStandbyCurrent: /CS>=VIHMIN,all banksidle;
IDD2F CKE>=VIHMIN;addressandothercontrol inputschangingonceperclockcycle,VIN 30 35 35 40 35 40 45 55 46 56 mA 1,2
=VREFfor DQ, DQSandDM.
PrechargeQuietStandbyCurrent:/CS>=VIHMIN,all banksidle;
IDD2Q CKE>=VIHMIN;addressandothercontrol inputsstable
at >= VIHMIN or <= VIL MAX; VIN = VREF for DQ, DQSand DM.
18 22 20 25 20 25 25 28 24 34 mA 1,2
IDD3P
ActivePower-DownStandbyCurrent: onebank active; power-downmode;
CKE<= VIL MAX; VIN= VREF for DQ, DQSand DM.
IDD3N
ActiveStandbyCurrent: onebank active; CS>=VIHMIN;
CKE>=VIHMIN;tRC=tRASMAX;DQ,DM, andDQSinputs
changing twice per clock cycle; address and control inputs changing
x4/x8
onceper clock cycle
x16
Operating Current: one bank active; BL2; reads; continuous burst;
addressandcontrol inputschangingonceperclockcycle;50%of
x4/x8
IDD4R _{dataoutputschangingoneveryclockedge;CL2forDDR200and}
DDR266(A), CL3 for DDR333 and DDR400; IOUT = 0mA
x16
Operating Current: one bank active; Burst = 2; writes; continuous _x4/x8
IDD4W
burst; address and control inputs changing once per clock cycle;
50%of dataoutputschangingoneveryclockedge;CL2for
DDR200 and DDR266(A), CL3 for DDR333 and DDR400
x16
13 16 15 18 15 18 18 21 17 24 mA 1,2
40 45 50 55 50 55 60 65 57 69 mA
1, 2
42 50 52 60 52 60 63 70 60 74 mA
79 95 95 115 95 115 110 140 115 145 mA
1, 2
89 110 107 130 107 130 124 160 140 175 mA
85 105 105 125 105 125 125 145 125 150 mA
1, 2
96 120 119 140 119 140 141 165 150 180 mA
IDD5 Auto-RefreshCurrent:tRC=tRFCMIN,distributedrefresh
126 170 135 180 135 180 144 190 155 195 mA 1,2
IDD6 Self-RefreshCurrent:CKE<=0.2V;external clockon
standardversion 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.6 2.6 mA
1, 2, 3
lowpower version 1.20 1.25 1.20 1.25 1.20 1.25 1.20 1.25 1.25 1.30 mA
Operating Current: four bank; four bank interleaving with burst x4/x8
IDD7 length4;
Refer tothefollowingpagefor detailedtest conditions.
x16
150 210 171 225 171 225 208 270 240 280
mA 1,2
158 220 180 235 180 235 218 285 260 310
1. IDDspecifications aretestedafter thedeviceis properly initializedandmeasured
at 100MHz for DDR200, 133MHz for DDR266(A) and166MHz for DDR333
2. Input slewrate=1V/ns.
3. Enables on-chiprefreshandaddress counters
4.Testconditionfortypical values: VDD=2.5V,Ta=25°C,testconditionformaximumvalues:testlimitatVDD=2.7V,Ta=10°C
Page 24 of 29
2003-01-10, V0.9