C167CR_00 Datasheet, PDF (86/464 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcont roller

C167CR
Derivatives
Interrupt and Trap Functions
Normal Interrupt Processing and PEC Service
During each instruction cycle one out of all sources which require PEC or interrupt
processing is selected according to its interrupt priority. This priority of interrupts and
PEC requests is programmable in two levels. Each requesting source can be assigned
to a specific priority. A second level (called “group priority”) allows to specify an internal
order for simultaneous requests from a group of different sources on the same priority
level. At the end of each instruction cycle the one source request with the highest current
priority will be determined by the interrupt system. This request will then be serviced, if
its priority is higher than the current CPU priority in register PSW.
Interrupt System Register Description
Interrupt processing is controlled globally by register PSW through a general interrupt
enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt
sources are controlled individually by their specific interrupt control registers (… IC).
Thus, the acceptance of requests by the CPU is determined by both the individual
interrupt control registers and the PSW. PEC services are controlled by the respective
PECCx register and the source and destination pointers, which specify the task of the
respective PEC service channel.
5.1.1 Interrupt Control Registers
All interrupt control registers are organized identically. The lower 8 bits of an interrupt
control register contain the complete interrupt status information of the associated
source, which is required during one round of prioritization, the upper 8 bits of the
respective register are reserved. All interrupt control registers are bit-addressable and all
bits can be read or written via software. This allows each interrupt source to be
programmed or modified with just one instruction. When accessing interrupt control
registers through instructions which operate on word data types, their upper 8 bits
(15 … 8) will return zeros, when read, and will discard written data.
The layout of the Interrupt Control registers shown below applies to each xxIC register,
where xx stands for the mnemonic for the respective source.
User’s Manual
5-6
V3.1, 2000-03