C167CR_00 Datasheet, PDF (270/464 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcont roller

C167CR
Derivatives
The High-speed Synchronous Serial Interface
Bit
SSCBM
SSCHB
SSCPH
SSCPO
SSCTEN
SSCREN
SSCPEN
SSCBEN
SSCAREN
SSCMS
SSCEN
Function (Programming Mode, SSCEN = ‘0’)
SSC Data Width Selection
0: Reserved. Do not use this combination.
1…15: Transfer Data Width is 2 … 16 bit (<SSCBM> + 1)
SSC Heading Control Bit
0: Transmit/Receive LSB First
1: Transmit/Receive MSB First
SSC Clock Phase Control Bit
0: Shift transmit data on the leading clock edge, latch on trailing edge
1: Latch receive data on leading clock edge, shift on trailing edge
SSC Clock Polarity Control Bit
0: Idle clock line is low, leading clock edge is low-to-high transition
1: Idle clock line is high, leading clock edge is high-to-low transition
SSC Transmit Error Enable Bit
0: Ignore transmit errors
1: Check transmit errors
SSC Receive Error Enable Bit
0: Ignore receive errors
1: Check receive errors
SSC Phase Error Enable Bit
0: Ignore phase errors
1: Check phase errors
SSC Baudrate Error Enable Bit
0: Ignore baudrate errors
1: Check baudrate errors
SSC Automatic Reset Enable Bit
0: No additional action upon a baudrate error
1: The SSC is automatically reset upon a baudrate error
SSC Master Select Bit
0: Slave Mode. Operate on shift clock received via SCLK.
1: Master Mode. Generate shift clock and output it via SCLK.
SSC Enable Bit = ‘0’
Transmission and reception disabled. Access to control bits.
User’s Manual
12-3
V3.1, 2000-03