C167CR_00 Datasheet, PDF (35/464 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcont roller

C167CR
Derivatives
Memory Organization
3
Memory Organization
The memory space of the C167CR is configured in a “Von Neumann” architecture. This
means that code and data are accessed within the same linear address space. All of the
physically separated memory areas, including internal ROM/Flash/OTP (where
integrated), internal RAM, the internal Special Function Register Areas (SFRs and
ESFRs), the address areas for integrated XBUS peripherals and external memory are
mapped into one common address space.
The C167CR provides a total addressable memory space of 16 MBytes. This address
space is arranged as 256 segments of 64 KBytes each, and each segment is again
subdivided into four data pages of 16 KBytes each (see Figure 3-1).
255
FF’FFFFH
254...129
128
127
80’0000H
126...65
64
63
40’0000H
62...12
11
0A’FFFFH
10
9
8
7
08’0000H
6
5
4
3
2
02’FFFFH
1
01’FFFFH
0
00’0000H
Total Address Space
16 MByte, Segments 255...0
Figure 3-1 Address Space Overview
User’s Manual
3-1
255...2
01’FFFFH
Begin of
Prog. Memory
above 32 KB
Alternate
ROM
Area
Data Page 3
01’8000H
01’0000H
Data Page 2
Internal
ROM
Area
Segments 1 and 0
64 + 64 Kbyte
00’0000H
MCA04325
V3.1, 2000-03