C167CR_00 Datasheet, PDF (187/464 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcont roller

C167CR
Derivatives
The External Bus Interface
9.3
Programmable Bus Characteristics
Important timing characteristics of the external bus interface have been made user
programmable to allow to adapt it to a wide range of different external bus and memory
configurations with different types of memories and/or peripherals.
The following parameters of an external bus cycle are programmable:
• ALE Control defines the ALE signal length and the address hold time after its falling
edge
• Memory Cycle Time (extendable with 1 … 15 waitstates) defines the allowable
access time
• Memory Tri-State Time (extendable with 1 waitstate) defines the time for a data
driver to float
• Read/Write Delay Time defines when a command is activated after the falling edge
of ALE
• READY Control defines, if a bus cycle is terminated internally or externally
Note: Internal accesses are executed with maximum speed and therefore are not
programmable.
External accesses use the slowest possible bus cycle after reset. The bus cycle
timing may then be optimized by the initialization software.
ALE
ADDR
RD/WR
DATA
ALE
ADDR
RD/WR
Figure 9-5
DATA
ALECTL
MCTC
Programmable External Bus Cycle
User’s Manual
9-12
MTTC
MCD02225
V3.1, 2000-03