C167CR_00 Datasheet, PDF (359/464 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcont roller

C167CR
Derivatives
The On-chip CAN Interface
CAN Interrupt Handling
The on-chip CAN module has one interrupt output, which is connected (through a
synchronization stage) to a standard interrupt node in the C167CR in the same manner
as all other interrupts of the standard on-chip peripherals. With this configuration, the
user has all control options available for this interrupt, such as enabling/disabling, level
and group priority, and interrupt or PEC service (see note below). The on-chip CAN
module is connected to an XBUS interrupt control register.
As for all other interrupts, the node interrupt request flag is cleared automatically by
hardware when this interrupt is serviced (either by standard interrupt or PEC service).
Note: As a rule, CAN interrupt requests can be serviced by a PEC channel. However,
because PEC channels only can execute single predefined data transfers (there
are no conditional PEC transfers), PEC service can only be used, if the respective
request is known to be generated by one specific source, and that no other
interrupt request will be generated in between. In practice this seems to be a rare
case.
Since an interrupt request of the CAN module can be generated due to different
conditions, the appropriate CAN interrupt status register must be read in the service
routine to determine the cause of the interrupt request. The interrupt identifier INTID (a
number) in the Port Control/Interrupt Register (PCIR) indicates the cause of an interrupt.
When no interrupt is pending, the identifier will have the value 00_H.
If the value in INTID is not 00_H, then there is an interrupt pending. If bit IE in the control/
status register is set also the interrupt signal to the CPU is activated. The interrupt signal
(to the interrupt node) remains active until INTID gets 00_H (i.e. all interrupt requests have
been serviced) or until interrupt generation is disabled (CSR.IE = ‘0’).
Note: The interrupt node is activated only upon a 0 → 1 transition of the CAN interrupt
signal. The CAN interrupt service routine should only be left after INTID has been
verified to be 00_H.
The interrupt with the lowest number has the highest priority. If a higher priority interrupt
(lower number) occurs before the current interrupt is processed, INTID is updated and
the new interrupt overrides the last one.
INTID is also updated when the respective source request has been processed. This is
indicated by clearing the INTPND flag in the respective object’s message control register
(MCRn) or by reading the status partition of register CSR (in case of a status change
interrupt). The updating of INTID is done by the CAN state machine and takes up to 6
CAN clock cycles (1 CAN clock cycle = 1 or 2 CPU clock cycles, detrmined by the
prescaler bit CPS), depending on current state of the state machine.
Note: A worst case condition can occur when BRP = 00_H AND the CAN controller is storing
a just received message AND the CPU is executing consecutive accesses to the CAN
module. In this rare case the maximum delay may be 26 CAN clock cycles.
The impact of this delay can be minimized by clearing bit INTPND at an early stage
User’s Manual
18-9
V3.1, 2000-03