C164CM_2 Datasheet, PDF (82/470 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CM/C164SM
Derivatives
Central Processing Unit (CPU)
Context Pointer CP
This non-bit addressable register is used to select the current register context. This
means that the CP register value determines the address of the first General Purpose
Register (GPR) within the current register bank of up to 16 wordwide and/or bytewide
GPRs.
CP
Context Pointer
SFR (FE10_H/08_H)
15 14 13 12 11 10 9 8 7 6 5
1111
cp
rrrr
rw
Reset Value: FC00_H
43210
0
r
Bit
Function
cp
Modifiable portion of register CP
Specifies the (word) base address of the current register bank.
When writing a value to register CP with bits CP.11 … CP.9 = ‘000’, bits
CP.11 … CP.10 are set to ‘11’ by hardware. In all other cases, all bits of
the bit field “cp” receive the written value.
Note: It is the user’s responsibility to ensure that the physical GPR address specified via
CP register plus short GPR address is always an internal RAM location. If this
condition is not met, unexpected results may occur.
• Do not set CP below the IRAM start address, i.e. 00’FA00_H/00’F600_H/00’F200_H
(referring to an IRAM size of 1/2/3 KByte)
• Do not set CP above 00’FDFE_H
• Be careful using the upper GPRs with CP above 00’FDE0_H
The CP register can be updated via any instruction capable of modifying an SFR.
Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR
address calculations of the instruction immediately following the instruction which
updated the CP register.
The Switch Context instruction (SCXT) allows saving the content of register CP on the
stack and updating it with a new value in only one machine cycle.
User’s Manual
4-25
V1.0, 2002-02