C164CM_2 Datasheet, PDF (202/470 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CM/C164SM
Derivatives
General Purpose Timer Unit
Timer 3 in Counter Mode
Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘001_B’. In counter mode timer T3 is clocked by a transition at the external input pin
T3IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and a negative transition at this pin. Bit field T3I in control
register T3CON selects the triggering transition (see Table 10-5).
Edge
Select
TxIN
TxEUD
Txl
TxUD
XOR
TxR
0
MUX
1
Core Timer Tx
Up/
Down
TxOTL
To auxiliary
Timers
Interrupt
Request
(TxIR)
T3IN = P5.3
T3EUD = P5.2
TxUDE
Figure 10-5 Block Diagram of Core Timer T3 in Counter Mode
MCB02030c
x=3
Table 10-5 GPT1 Core Timer T3 (Counter Mode) Input Edge Selection
T3I
Triggering Edge for Counter Increment/Decrement
000
None. Counter T3 is disabled
001
Positive transition (rising edge) on T3IN
010
Negative transition (falling edge) on T3IN
011
Any transition (rising or falling edge) on T3IN
1XX
Reserved. Do not use this combination
For counter operation, pin T3IN must be configured as input; the respective direction
control bit DPx.y must be set to ‘0’. The maximum input frequency allowed in counter
mode is f_CPU/16. To ensure that a transition of the count input signal applied to T3IN is
recognized correctly, its level should be held high or low for at least 8 f_CPU cycles before
it changes.
User’s Manual
10-8
V1.0, 2002-02