C164CM_2 Datasheet, PDF (179/470 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CM/C164SM
Derivatives
External Bus Interface
ALE Length Control
The length of the ALE signal and the address hold time after its falling edge are
controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to ‘1’,
external bus cycles accessing the respective address window will have their ALE signals
prolonged by half a CPU clock (1 TCL). Also, the address hold time after the falling edge
of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer
within a bus cycle refers to the same CLKOUT edges as usual (the data transfer is
delayed by one CPU clock). This allows more time for the address to be latched.
Note: ALECTL0 is ‘1’ after reset to select the slowest possible bus cycle, the other
ALECTLx are ‘0’ after reset.
ALE
BUS (P0)
RD
Normal Multiplexed
Bus Cycle
Address
Data/Instr.
Lengthened Multiplexed
Bus Cycle
Setup
Hold
Address
Data/Instr.
BUS (P0)
Address
Data
WR
Figure 9-6 ALE Length Control
Address
Data
MCD02235M
User’s Manual
9-10
V1.0, 2002-02