C164CM_2 Datasheet, PDF (257/470 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CM/C164SM
Derivatives
Real Time Clock
RTC Register Access
The actual value of the RTC is indicated by the three registers T14, RTCL and RTCH.
As these registers are concatenated to build the RTC counter chain, internal overflows
occur while the RTC is running. When reading or writing the RTC value, such internal
overflows must be taken into account to avoid reading/writing corrupted values. For
example, reading/writing 0000_H to RTCH and then accessing RTCL will produce a
corrupted value as RTCL may overflow before it can be accessed. In this case, however,
RTCH would be 0001_H. The same precautions must be taken for T14 and T14REL.
RTC Interrupt Generation
The RTC interrupt shares the XPER3 interrupt node with the PLL/OWD interrupt. This is
controlled by the interrupt subnode control register ISNC. The interrupt handler can
determine the source of an interrupt request via the separate interrupt request and
enable flags (see Figure 14-3) provided in register ISNC.
Note: If only one source is enabled, no additional software check is required, of course.
PLL/OWD
Interrupt
T14
Interrupt
PLLIR
Intr. Request
PLLIE
Intr. Enable
RTCIR
Intr. Request
RTCIE
Intr. Enable
Register ISNC
XPER3
Interrupt
Node
Interrupt
Controller
Register XP3IC
MCA04464
Figure 14-3 RTC Interrupt Logic
If T14 interrupts are to be used both stages the interrupt node (XP3IE = ‘1’) and the RTC
subnode (RTCIE = ‘1’) must be enabled.
Please note that the node request bit XP3IR is automatically cleared when the interrupt
handler is vectored to, while the subnode request bit RTCIR must be cleared by
software.
User’s Manual
14-3
V1.0, 2002-02