C164CM_2 Datasheet, PDF (30/470 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller

C164CM/C164SM
Derivatives
Architectural Overview
Peripheral Timing
Internal operation of the CPU and peripherals is based on the CPU clock (f_CPU). The on-
chip oscillator derives the CPU clock from the crystal or from the external clock signal.
The clock signal gated to the peripherals is independent from the clock signal that feeds
the CPU. During Idle mode, the CPU’s clock is stopped while the peripherals continue
their operation. Peripheral SFRs may be accessed by the CPU once per state. When an
SFR is written to by software in the same state where it is also to be modified by the
peripheral, the software write operation has priority. Further details on peripheral timing
are included in the specific sections describing each peripheral.
Programming Hints
Access to SFRs
All SFRs reside in data page 3 of the memory space. The following addressing
mechanisms allow access to the SFRs:
• Indirect or direct addressing with 16-bit (mem) addresses must guarantee that the
used data page pointer (DPP0 … DPP3) selects data page 3.
• Accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx
pointers instead of the data page pointers.
• Short 8-bit (reg) addresses to the standard SFR area do not use the data page
pointers but directly access the registers within this 512-Byte area.
• Short 8-bit (reg) addresses to the extended ESFR area require switching to the
512-Byte Extended SFR area. This is done via the EXTension instructions EXTR,
EXTP(R), EXTS(R).
Byte write operations to wordwide SFRs via indirect or direct 16-bit (mem) addressing
or byte transfers via the PEC force zeros in the non-addressed byte. Byte write
operations via short 8-bit (reg) addressing can access only the low byte of an SFR and
force zeros in the high byte. It is therefore recommended, to use the bit field instructions
(BFLDL and BFLDH) to write to any number of bits in either byte of an SFR without
disturbing the non-addressed byte and the unselected bits.
Reserved Bits
Some of the bits which are contained in the C164CM’s SFRs are marked as ‘Reserved’.
User software should never write ‘1’s to reserved bits. These bits are currently not
implemented and may be used in future products to invoke new functions. In that case,
the active state for those new functions will be ‘1’, and the inactive state will be ‘0’.
Therefore writing only ‘0’s to reserved locations allows portability of the current software
to future devices. After read accesses, reserved bits should be ignored or masked out.
User’s Manual
2-13
V1.0, 2002-02