HYS72D32300GBR Datasheet, PDF (8/38 Pages) Infineon Technologies AG – 184-Pin Registered Double Data Rate SDRAM Module

HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
2
Pin Configuration
The pin configuration of the Registered DDR SDRAM
DIMM is listed by function in Table 3 (184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
numbering is depicted in Figure 1.
Table 3 Pin Configuration of RDIMM
Pin# Name Pin Buffer Function
Type Type
Clock Signals
137 CK0 I
SSTL Clock Signal
138 CK0 I
SSTL Complement Clock
21 CKE0 I
SSTL Clock Enable Rank 0
111 CKE1 I
SSTL Clock Enable Rank 1
Note: 2-rank module
NC NC SSTL Note: 1-rank module
Control Signals
157 S0
I
SSTL Chip Select of Rank 0
158 S1
I
SSTL Chip Select of Rank 1
Note: 2-ranks module
NC NC –
Note: 1-rank module
154 RAS I
SSTL Row Address Strobe
65 CAS I
SSTL Column Address
Strobe
63 WE I
SSTL Write Enable
10 RESET I
LV- Register Reset
CMOS Forces registered
inputs low
Note: For
detailed
description of the
Power Up and
Power
Management see
the Application
Note at the end of
data sheet
Address Signals
59 BA0 I
52 BA1 I
SSTL Bank Address Bus
SSTL ^1:0
48 A0
I
SSTL Address Bus 11:0
43 A1
I
SSTL
41 A2
I
SSTL
130 A3
I
SSTL
37 A4
I
SSTL
32 A5
I
SSTL Address Bus 11:0
Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin Buffer Function
Type Type
125 A6
I
SSTL Address Bus 11:0
29 A7
I
SSTL
122 A8
I
SSTL
27 A9
I
SSTL
141 A10 I
SSTL
AP
I
SSTL
118 A11 I
SSTL
115 A12 I
SSTL Address Signal 12
Note: Module based on
256 Mbit or larger
dies
NC
NC –
Note: 128 Mbit based
module
167 A13 I
SSTL Address Signal 13
Note: 1 Gbit based
module
NC
NC –
Note: Module based on
512 Mbit
or
smaller dies
Data Sheet
8
Rev. 1.0, 2004-03