HYS72D32300GBR Datasheet, PDF (11/38 Pages) Infineon Technologies AG – 184-Pin Registered Double Data Rate SDRAM Module

HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
Pin Configuration
Table 3 Pin Configuration of RDIMM (cont’d)
Pin# Name Pin Buffer Function
Type Type
3, V_SS
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
GND –
Ground Plane
Other Pins
82 V_DDID O
OD V_DD Identification
Note: Pin in tristate,
indicating V_DD
and V_DDQ nets
connected on
PCB
9, NC
16,
17,
71,
75,
76,
90,
101,
102,
103,
113,
163,
173
NC –
Not connected
Pins not connected on
Infineon RDIMM’s
Table 4
Abbreviations for Pin Type
Abbreviation Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 5
Abbreviations for Buffer Type
Abbreviation Description
SSTL
Serial Stub Terminalted Logic (SSTL2)
LV-CMOS Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Data Sheet
11
Rev. 1.0, 2004-03