HYS72D32300GBR Datasheet, PDF (24/38 Pages) Infineon Technologies AG – 184-Pin Registered Double Data Rate SDRAM Module

HYS72D[128/64/32][300/320]GBR–[5/6]–C
Registered Double Data Rate SDRAM
5
SPD Contents
SPD Contents
Table 13 SPD Codes for HYS72D[128/64/32][300/320]GBR–5–C
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Label Code
Jedec SPD Revision
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
Data Width (MSB)
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
512 MB
×72
1 Rank
PC3200R–30331
Rev 1.0
HEX
80
08
07
0D
0B
01
48
00
04
50
50
02
82
04
04
01
0E
04
1C
01
02
26
C1
60
50
75
512 MB
×72
2 Ranks
PC3200R–30331
Rev 1.0
HEX
80
08
07
0D
0A
02
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
26
C1
60
50
75
256 MB
×72
1 Rank
PC3200R–30331
Rev 1.0
HEX
80
08
07
0D
0A
01
48
00
04
50
50
02
82
08
08
01
0E
04
1C
01
02
26
C1
60
50
75
Data Sheet
24
Rev. 1.0, 2004-03
07302003-2MI6-FOP1