HYE25L256160AC Datasheet, PDF (8/55 Pages) Infineon Technologies AG – 256-Mbit Mobile-RAM

HYE25L256160AC
256-Mbit Mobile-RAM
Pin Configuration
Table 3 Input/Output Signals (cont’d)
Pin Symbol Type Polarity Function
A2 DQ15 Input/ Active Data Input/Output
B1 DQ14 ^{Output High Data bus operates in the same manner as on conventional DRAMs.}
B2 DQ13
C1 DQ12
C2 DQ11
D1 DQ10
D2 DQ9
E1 DQ8
E9 DQ7
D8 DQ6
D9 DQ5
C8 DQ4
C9 DQ3
B8 DQ2
B9 DQ1
A8 DQ0
F1 UDQM Input
E8 LDQM
Active
High
Data Input/Output Mask
UDQM and LDQM are output disable signals during read mode and input mask
signals for write data. In Read mode, U/LDQM have a latency of two clock
cycles and control the output buffers like low active output enable signals. In
Write mode, U/LDQM have a latency of zero and operate as a word mask by
allowing input data to be written if it is low but blocks the write operation if the
respective DQM is high.
UDQM controls the upper byte and LDQM controls the lower byte.
E2 NC
–
–
Not Connected
No internal electrical connection is present.
A7, V_DDQ
B3,
C7,
D3
Supply –
DQ Power Supply
A3 V_SSQ
B7
C3
D7
Supply –
DQ Ground
A9 V_DD
E4
J9
Supply –
Power Supply
A1 V_SS
E3
J1
Supply –
Ground
Data Sheet
8
V1.1, 2003-04-16