HYE25L256160AC Datasheet, PDF (25/55 Pages) Infineon Technologies AG – 256-Mbit Mobile-RAM

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Timing Diagrams
Figure 5 Bank Activate Command Cycle
Figure 6 Burst Read Operation
Figure 7 Read Interrupted by a Read
Read to Write Interval
– Figure 8 Read to Write Interval
– Figure 9 Minimum Read to Write Interval
– Figure 10 Non-Minimum Read to Write Interval
Figure 11 Burst Write Operation
Write and Read Interrupt
– Figure 12 Write Interrupted by a Write
– Figure 13 Write Interrupted by Read
Burst Write & Read with Auto-Precharge
– Figure 14 Burst Write with Auto-Precharge
– Figure 15 Burst Read with Auto-Precharge
AC- Parameters
– Figure 16 AC Parameters for a Write Timing
– Figure 17 AC Parameters for a Read Timing
Figure 18 Mode Register Set
Figure 19 Power on Sequence and Auto Refresh (CBR)
Clock Suspension (using CKE)
– Figure 20 Clock Suspension During Burst Read CAS Latency = 2
– Figure 21 Clock Suspension During Burst Read CAS Latency = 3
– Figure 22 Clock Suspension During Burst Write CAS Latency = 2
– Figure 23 Clock Suspension During Burst Write CAS Latency = 3
Figure 24 Power Down Mode and Clock Suspend
Figure 25 Self Refresh (Entry and Exit)
Figure 26 Auto Refresh (CBR)
Random Column Read ( Page within same Bank)
– Figure 27 CAS Latency = 2
– Figure 28 CAS Latency = 3
Random Column Write ( Page within same Bank)
– Figure 29 CAS Latency = 2
– Figure 30 CAS Latency = 3
Random Row Read (Interleaving Banks) with Precharge
– Figure 31 CAS Latency = 2
– Figure 32 CAS Latency = 3
Random Row Write (Interleaving Banks) with Precharge
– Figure 33 CAS Latency = 2
– Figure 34 CAS Latency = 3
Precharge Termination of a Burst
– Figure 35 CAS Latency = 2
Deep Power Down Mode
– Figure 36 Deep Power Down Mode Entry
– Figure 37 Deep Power Down Mode Exit
Data Sheet
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HYE25L256160AC
256-Mbit Mobile-RAM
Timing Diagrams
V1.1, 2003-04-16