TLE8262E Datasheet, PDF (75/93 Pages) Infineon Technologies AG – Universal System Basis Chip HERMES Rev. 1.0

TLE8262E
Serial Peripheral Interface
15.5.2.2 Interrupt Register Encoder
Table 16 lists all interrupts the SBC can generates. The microcontroller should read the correct register to release
the INT pin. By default, all interrupt sources are enabled. The microcontroller can decide to inhibit a specific
interrupt source.
Table 16 Interrupt Register encoder ¹⁾
CS Bit Name
Default Default
Value Value
(INPUT) (OUT)
Data Input
Data Output
Configuration select 000 (Wake register interrupt)
000 WK CAN
1
0
Interrupt enabled (1) disabled Wake on CAN (1)
(0) for wake event on CAN
WKLINx
1
0
Interrupt enabled (1) disabled Wake on LINx (1)
(0) for wake event on LIN
WK 1 WK pin 11
00
Interrupt enabled (1) disabled Wake on WK pin
WK 0 WK pin
(0) for wake pin event.
00 No wake
00 No interrupt
10 Interrupt for a LOW to HIGH
10 Interrupt for a LOW to HIGH transition on WK
transition on WK
01 Interrupt for HIGH to LOW
01 Interrupt for HIGH to LOW transition on WK
transition on WK
11 Interrupt for both HIGH to
11 Interrupt for both HIGH to LOW and LOW to HIGH on WK
LOW and LOW to HIGH on WK
Cyclic WK
n.a
0
n.a
Cyclic WK (1)
INT
n.a
0
n.a
Indicates that there is a status
bit or uncleared event in
configuration select 001 and/or
010. If set read the two register
Data Sheet
75
Rev. 1.0, 2009-03-31