TLE8262E Datasheet, PDF (14/93 Pages) Infineon Technologies AG – Universal System Basis Chip HERMES Rev. 1.0

TLE8262E
State Machine
Table 2 SBC Restart Mode Entry Reasons and Actions
SBC Mode and Configuration Entering reason
Mode
Config
n.a
Init Mode time-out
Actions
LH output
ON
V_cc1µC
RO
remains ON LOW
Init Mode
n.a.
Reset low from
outside
Unchanged remains ON LOW
config 1/3 Reset clamped
ON
remains ON LOW
n.a
undervoltage reset unchanged ramping up LOW
config 1
ON
Normal¹⁾
config 3
config 4
WD trigger failure
OFF after 1st
ON after 2nd
remains ON LOW
OFF after 1st
n.a.
Reset low from
outside
Unchanged remains ON LOW
config 1/3 Reset clamped
ON
remains ON LOW
n.a
undervoltage reset unchanged remains ON LOW
n.a
SPI cmd
unchanged remains ON LOW
Software Flash n.a
WD trigger failure unchanged remains ON LOW
n.a.
Reset low from
outside
Unchanged remains ON LOW
config 1/3 Reset clamped
ON
remains ON LOW
Sleep
n.a
Wake-up event
unchanged ramping up LOW
n.a
undervoltage reset unchanged ramping up LOW
config 1
ON
Stop¹⁾
config 3
config 4
WD trigger failure
OFF after 1st
ON after 2nd
remains ON LOW
OFF after 1st
n.a.
Reset low from
Unchanged remains ON LOW
outside
config 1/3 Reset clamped
ON
remains ON LOW
Fail-Safe
n.a.
Wake-up event
ON
ramping up LOW
Software
Development
Mode
n.a
n.a.
config 1/3
undervoltage reset
Reset low from
outside
Reset clamped
unchanged
Unchanged
ON
ramping up LOW
remains ON LOW
remains ON LOW
1) Config 2 will never enter Restart Mode in case of WD failure but directly Fail-Safe Mode
2) Goes to Fail-Safe Mode after the second consecutive failure
SPI Out Bits
LH 0..2
RM 0..1
LH 0..2
RM 0..1
LH 0..2
RM 0..1 after 1st
LH 0..2 after 2nd
RM 0..1 after 1st²⁾
RM 0..1
LH 0..2
RM 0..1
RM 0..1
RM 0..1
RM 0..1
LH 0..2
WK bits register
RM 0..1
LH 0..2
RM 0..1 after 1st
LH 0..2 after 2nd
RM 0..1 after 1st²⁾
RM 0..1
LH 0..2
LH 0..2
RM 0..1
RM 0..1
LH 0..2
Data Sheet
14
Rev. 1.0, 2009-03-31