TLE8262E Datasheet, PDF (13/93 Pages) Infineon Technologies AG – Universal System Basis Chip HERMES Rev. 1.0

TLE8262E
State Machine
4.2.7 SBC Software Flash Mode
SBC Software Flash Mode is similar to SBC Normal Mode regarding voltage regulators. In this mode, the Limp
Home output can be set to active LOW via SPI and the communication on CAN and LIN modules is activated to
receive flash data. In the LIN module the slope control mechanism is switched off. The Watchdog configuration is
fixed to the settings used before entering the SBC SW Flash Mode. When the device comes from SBC Normal
Mode, a reset is generated at the transition.
From the SBC Software Flash Mode, the SBC goes into SBC Restart Mode, the config setting has no influence
on the behavior. A mode change to SBC Restart Mode can be caused by a SPI command, a time-out or Window
Watchdog failure or an undervoltage reset. When leaving the SBC Software Flash Mode a reset is generated.
4.2.8 SBC Restart Mode
They are multiple reasons to enter the SBC Restart Mode and multiple SBC behaviors described in Table 2.
In any case, the purpose of the SBC Restart Mode is to reset the microcontroller.
• From SBC SW Flash Mode, it is used to start the new downloaded code.
• From SBC Normal, SBC Stop Mode and SBC SW Flash Mode it is reached in case of undervoltage on V_cc1µC,
or due to incorrect Watchdog triggering.
• From SBC Sleep Mode it is used to ramp up V_cc1µC after wake
• From SBC Init Mode, it is used to avoid the system to remain undefined.
• From SBC Fail-safe Mode it is used to ramp up V_cc1µC after wake or cool down of Vcc1µC.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode. The delay time t_RDx is programmable
by the “Reset delay” SPI bit. The Reset output (RO) is released at the transition. SBC Restart Mode is left
automatically by the SBC without any microcontroller influence. The first SPI output data will provide information
about the reason for entering Restart Mode. The reason for entering Restart Mode is stored and kept until the
microcontroller reads the corresponding “LH0..2” or “RM0..1” SPI bits. In case of a wake up from Sleep Mode the
wake source is seen at the interrupt bits (Configuration select 000), an interrupt is not generated.
Entering or leaving the SBC Restart Mode will not result in deactivation of the Limp Home output (if activated).
The first SPI output data when going to SBC Normal Mode will always indicate the reason for the SBC Restart
event.
Data Sheet
13
Rev. 1.0, 2009-03-31