C868 Datasheet, PDF (66/82 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

C868
Table 15 Power Saving Modes Overview
Mode Entering
Leaving by
Remarks
Idle
Mode
ORL PCON,#01_H
Occurance of any
enabled interrupt
Hardware Reset
CPU clock is stopped;
CPU maintains its
data;
peripheral units are
active (if enabled) and
provided with clock
Slow
Down
Mode
In normal mode:
ORL PCON,#10_H
ANL PCON,#0EF_H
or Hardware Reset
Internal clock rate is
reduced to a
configurable factor of
1_{/2 to} 1_{/32 of the}
system clock rate
With idle mode:
ORL PCON,#11_H
Occurance of any
enabled interrupt to
exit idle mode and
the instruction
ANL PCON,#0EF_H
to terminate slow
down mode
Hardware Reset
CPU clock is stopped;
CPU maintains all its
data;
Peripheral units are
active (if enabled) and
provided with a
configurable factor of
1_{/2 to} 1_{/32 of the}
system clock rate
Software
Power
Down
mode
With external wake-up
capability from power down
enabled
ORL PMCON0,#01_H
(to wake-up via pin INT0)
or
ORL PMCON0,#03_H
(to wake-up via pin RxD)
ORL PCON,#02_H
Hardware Reset Oscillator is stopped;
When INT0 or RxD ^{Contents of on-chip}
goes low for at least ^{RAM and SFR’s are}
10 µs (latch phase). ^maintained
But it is desired that
the corresponding
pin must be held at
high level during the
power down mode
entry and up to the
wake-up.
With external wake-up
capability from power down
disabled
ORL PCON,#02_H
Hardware Reset
Data Sheet
66
V 1.0, 2003-05