C868 Datasheet, PDF (22/82 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

C868
The PLL output frequency is determined by:
f_PLL = f_VCO / K =
15
K
×
f_OSC
[1]
The range for the VCO frequency is given by:
100 MHz ≤ f_VCO ≤ 160 MHz
[2]
The relationship between the input frequency and VCO frequency is given by:
f_VCO = 15 × f_OSC
[3]
This gives the range for the input frequency which is given by:
6.67 MHz ≤ f_OSC ≤ 10.67 MHz
[4]
Table 5
Output Frequencies f_PLL Derived from Various Output Factors
K-Factor
Selected KDIV
Factor
f_PLL
Duty
Jitter
f_VCO = f_VCO = ^{Cycle [%]}
100 MHz 160 MHz
2
000_B
50
80
50
4
010_B
25
40
50
5¹⁾
011_B
20
32
40
6
100_B
16.67 26.67 50
8
101_B
12.5
20
50
9¹⁾
110_B
11.11 17.78 44
10
111_B
10
16
50
16
001_B
6.25
10
50
linear depending on f_VCO
at f_VCO =100MHz: +/-300ps
at f_VCO =160MHz: +/-250ps
additional jitter for odd Kdiv
factors tbd.
1) _{These odd factors should not be used (not tested because off the unsymmetrical duty cycle).}
2) Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz.
Data Sheet
22
V 1.0, 2003-05