C868 Datasheet, PDF (62/82 Pages) Infineon Technologies AG – 8-Bit Single-Chip Microcontroller

C868
lf two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. lf requests of the same priority level are
received simultaneously, an internal polling sequence determines which request is to be
serviced first. Thus, within each priority level there is a second priority structure
determined by the polling sequence. This is illustrated in Table 13
.
Table 13
Interrupt Source Structure
Interrupt Priority Bits
Group of Interrupt
Group
Interrupt Source Priority
High Priority
Priority
0
IP0.0
EXINT0 IADC
Priority
Low
High
1
IP0.1
TF0
EXINT2
2
IP0.2
EXINT1 EXINT3 INP0¹⁾
3
IP0.3
4
IP0.4
TF1
RI + TI
INP1¹⁾
INP2¹⁾
5
IP0.5
TF2
Low
INP3¹⁾
1) _{Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/}
compare ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F.
The other flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE.
Within a column, the topmost interrupt is serviced first, then the second and the third,
when available. The interrupt groups are serviced from left to right of the table. A low-
priority interrupt can itself be interrupted by a higher-priority interrupt, but not by another
interrupt of the same or a lower priority. An interrupt of the highest priority level cannot
be interrupted by another interrupt source.
Data Sheet
62
V 1.0, 2003-05